Chemical mechanical polishing (CMP) has become an indispensable step in the fabrication of integrated circuit (IC) devices. In some steps of the fabrication process of ICs, later layers cannot be applied to a semiconductor substrate unless an earlier applied layer presents a planar surface. A CMP process is used to planarize such layers. In a step of the fabrication process, it may be desired to obtain a planar surface on an oxide layer. Alternatively, in a different step in fabricating a semiconductor device, a conformal layer of metal is deposited in blanket manner over a dielectric layer to fill vias therein. Then, by a CMP process, the blanket metal layer is polished down to the surface of the dielectric layer. In such a CMP process, it is important for the removal rates of the metal and dielectric materials to be dissimilar in order that polishing stops at the dielectric so that the metal inside the vias does not become overly "dished", i.e. overly removed below the upper surface of the dielectric layer, nor does the dielectric layer become overly thinned, either of which may lead to failure at a later time.
Conventionally, the chemical composition of the slurry is selected in order to adjust a removal rate according to the composition of a specific layer and features therein to be planarized. Apart from the chemical composition of the slurry provided to the CMP tool, two mechanical parameters play a critical role in determining the removal rate. These are the rotational velocity between the wafer and the polishing pad, and the downforce applied to press the wafer against the polishing pad. An increase in either the rotational velocity or the downforce results in a higher removal rate. Conversely, a decrease in the rotational velocity or the downforce results in a lower removal rate.
Currently available CMP polishers process only one or at most a few wafers at one time. The number of wafers which can be polished at one time is limited because conventional CMP polishers require the entire surface of each wafer to be placed in contact with the polishing pad. At current 200 mm wafer diameters, some existing CMP tools polish at most two wafers concurrently. A very large CMP polisher can polish as many as five 200 mm wafers on a single large disc-shaped polishing pad at one time.
With reference to FIG. 14, CMP is conventionally performed on equipment having a large rotating disc-shaped platen 118 of approximately 60 cm in diameter. A wafer 114 is held face down by a carrier 116 on a pad 119 covering the rotating platen 118. The wafer 114 is positioned between the outer disc perimeter 121 and an inner circle 123 at a set radius R from the center 125. Because the rotational velocity of the platen 118 is higher near the outer perimeter 121 of the platen than at the inner circle 123, the wafer is rotated during polishing in order to reduce position-dependent velocity variations which could result in polishing rate differentials at different locations on the wafer surface. However, despite this practice, a difference in rotational velocity still remains between the outer perimeter of the wafer and points near the wafer center. Consequently, a consistent polishing rate is not achieved between the outer perimeter and the interior surface of the wafer.
Because of this difference in rotational velocity at different wafer locations, it is considered undesirable to perform CMP at rotational velocities greater than 140 rpm. The rotational velocity of the disc platen in conventional CMP polishers is generally kept within a range between 10 and 140 rpm.
At conventional platen rotational velocities of 10 to 140 rpm, a force of at least 5 and up to 9 psi must be applied by a wafer carrier 116 to press the wafer towards the platen 118 ("downforce") in order to perform CMP to attain even a marginal wafer processing rate. The application of a downforce of 5 to 9 psi is not uncommon to achieve desirable process throughput. A known consequence of high downforce at the wafer/platen interface is a tendency for differentials in the removal rates of different composition features to increase. Higher downforce results in increased dishing of metal features within an oxide layer, and ultimately reduced planarity when polishing layers which contain features of different composition or pattern density.
Wafer throughput is one measure of the desirability of a CMP tool. There are other measures too. Optimally, CMP tools should be inexpensive to own and operate, occupy little space in a semiconductor foundry, polish to adequate and consistent local planarity, as well as global uniformity, and provide high and consistent throughput.
Existing CMP polishers are larger and more expensive than necessary and provide much lower throughput than that which is made possible by the multi-level polishing tool of the present invention disclosed in the following.
It is therefore an object of the present invention to provide a CMP polisher which provides greater throughput than existing CMP polishers.
A further object of the present invention is to provide a CMP polisher which is smaller than existing CMP polishers.
Another object of the present invention is to provide a CMP polisher which is less expensive to own and operate than existing CMP polishers.
Still another object of the present invention is to provide a CMP polisher which processes wafers in a consistent, quality manner.
Another object of the present invention is to provide a CMP polisher which polishes to superior planarity than that provided by existing CMP polishers.
An additional object of the present invention is to provide a fully integrated CMP polisher which performs in-situ post measurements and endpoint detection as well as wafer clean and dry operations.